As India sharpens its focus on building a strong semiconductor ecosystem, the fabless model is emerging as a practical and scalable path forward. In this interview, Nikul Shah, Co- Founder & CEO, IndeSemic, discusses with Anannya Saraswat, Correspondent, APAC Media and CXO Media, what it takes to build a globally competitive fabless semiconductor company—one that stays asset-light, capital efficient, and closely aligned with real market demand.
The conversation explores how design, strong partnerships, and policy support can help Indian chip firms move from niche players to global contenders.
What makes IndieSemic’s approach different from other fabless design firms globally?
At IndieSemiC, our differentiation lies in being system-led rather than IP-led. While many global fabless firms focus narrowly on selling standalone chip IP, we design application-specific silicon tightly integrated with system platforms, firmware, and reference designs. This significantly reduces customer integration time by 30–40%.
We focus on India-relevant and emerging-market use cases such as industrial automation, EV subsystems, smart energy, and edge AI, where volumes are scalable, but requirements are cost-sensitive. Our design philosophy prioritises mature-node optimisation (28nm–65nm), which still accounts for over 60% of global semiconductor volumes, rather than chasing bleeding-edge nodes. This allows us to keep NRE costs under USD 8–12 million per chip versus USD 50 million-plus at advanced nodes.
Finally, our teams are India-based, giving us a structural cost advantage of 35–45% compared to US or European peers, without compromising design quality.
What are the biggest cost drivers in your design cycle?
In a fabless model, the largest cost drivers are engineering manpower, EDA tool licensing, IP blocks, and silicon validation. Engineering talent typically accounts for nearly 45–50% of total design costs, especially during architecture and verification phases. EDA tools from global vendors can cost USD 3–5 million annually for a mid-sized design program. Third-party IP, such as CPU cores, memory controllers, and high-speed interfaces, adds another 20–25% to the bill of materials. Tape-out, packaging, and multi-shuttle silicon validation can range from USD 1–2 million per iteration, depending on node and complexity.
At IndieSemiC, we actively control these costs by reusing modular design blocks across products, adopting open standards where viable, and planning first-time-right tape-outs. This approach helps us keep our overall product development cycle within 18–24 months, compared to industry averages of 30 months.
Without owning fabrication facilities, how does IndieSemic manage capital efficiency?
Not owning fabs is central to capital efficiency. A greenfield semiconductor fab today requires USD 8–12 billion in capital expenditure, which is economically unviable for most design firms. IndieSemiC operates a fab-agnostic strategy, working with multiple global foundries to match product requirements with optimal cost-performance nodes. We use multi-project wafers (MPWs) in early stages, reducing initial silicon costs by up to 70%. Our balance sheet remains asset-light, with capital deployed primarily into R&D, which delivers a higher return on capital employed. We also align customer co-development and volume commitments before full-scale production, improving cash-flow predictability. As a result, our burn rate per product is typically 40–50% lower than vertically integrated peers. This model allows us to scale across multiple product lines without dilutive capital raises or long payback cycles.
How do you build demand visibility for your products?
Demand visibility is built well before tape-out. At IndieSemiC, we work closely with OEMs, Tier-1 suppliers, and system integrators during the concept and specification stage. Over 60% of our current pipeline is driven by customer-led problem statements rather than speculative design. We use long-term supply agreements and design-win commitments to anchor volumes for the first 3–5 years of a product’s lifecycle.
Additionally, our focus on industrial, automotive subsystems, and energy infrastructure gives us access to predictable, long-cycle demand, unlike more volatile consumer electronics. We also track government-led deployments in smart grids, EV charging, and industrial digitisation, which in India alone represent a multi-billion-dollar opportunity. This disciplined approach allows us to forecast revenues with greater accuracy and reduce inventory and obsolescence risks.
What role do partnerships play in your revenue and product planning? Which types of partnerships have been most valuable – design houses, foundries, OEMs, or others?
Partnerships are fundamental to our model. Foundry partnerships enable access to stable mature-node capacity at competitive pricing, while OSAT partners help optimise packaging costs, which can impact 10–15% of the final chip cost.
OEM and Tier-1 partnerships are the most valuable commercially, as they provide early volume commitments and roadmap alignment. Design ecosystem partners, including EDA vendors and IP providers, help us shorten development cycles by 20–25%. We also collaborate with academic institutions and R&D labs to build future-ready talent pipelines.
Revenue planning is tightly linked to these partnerships, with co-developed products contributing nearly 70% of projected revenues over the next three years. This ecosystem-driven approach reduces go-to-market risk and ensures that our silicon is commercially relevant from day one.
What markets do you see as the biggest opportunities for IndieSemic?
The strongest opportunities lie in industrial electronics, EV subsystems, smart energy, and edge AI. Globally, industrial and automotive semiconductors together represent over USD 200 billion in annual market size and are growing at an 8–10% CAGR. In India, EV penetration is expected to cross 30% for two- and three-wheelers by 2030, driving demand for motor control, battery management, and power ICs.
Smart grid and renewable energy deployments are expanding rapidly, supported by public investments exceeding USD 100 billion this decade. These segments favour long product lifecycles, stable volumes, and mature-node silicon, precisely where IndieSemiC is positioned. We also see export opportunities in Southeast Asia and the Middle East, where infrastructure-led electronics demand is rising steadily.
At the recent India AI Impact Summit, the Ministry of Electronics and Information Technology announced its plans to build billion-dollar fabless semiconductor companies in India. How realistic is that goal in the current ecosystem, and what concrete steps do you think are still needed to turn that vision into commercially viable, globally competitive companies?
The vision announced at the India AI Impact Summit by the Ministry of Electronics and Information Technology is ambitious but achievable.
India already contributes nearly 20% of the world’s semiconductor design workforce, yet captures less than 5% of global fabless revenues. To bridge this gap, scale capital, predictable demand, and global market access are critical. Design-linked incentives under India’s semiconductor mission, part of the Rs. 76,000 crore overall outlay, are a strong start. However, India needs deeper late-stage growth capital, stronger IP monetisation frameworks, and anchor customers willing to source at scale. If these pieces come together, building USD 1 billion fabless firms over the next 7–10 years is realistic.
What specific opportunities does this open up for IndieSemic in terms of funding, partnerships, market access, or product expansion over the next few years?
This policy push significantly expands IndieSemiC’s opportunity set.
On funding, access to design-linked incentives and strategic capital reduces dilution and accelerates multi-product roadmaps. On partnerships, it improves our ability to collaborate with global OEMs looking to diversify supply chains beyond traditional geographies. Market access expands through government-backed deployments in energy, mobility, and digital infrastructure, creating early scale opportunities.
We also see scope to expand into adjacent product lines—such as platform-based chip families, without proportionate increases in R&D spend. Over the next three to five years, these factors could enable 2–3x revenue growth with sustainable margins. For us, this ecosystem momentum is not just policy support; it’s a structural shift that aligns well with our long-term strategy.
